Chapter 208 Are you preparing to start a laptop price war?

Just like most technologies in this world, different technical routes can eventually achieve the same performance.

Just like a rocket booster, if one thrust is not enough, then four will be added.

certainly.

Chip stacking packaging technology does not simply superimpose two 28nm chips to achieve the performance of a 14nm chip by stacking them together. If it is really that simple, then major foundry manufacturers will have already applied it.

In fact, top chip stacking and packaging technology is very difficult.

Not only does the chip design complexity increase by a hundred times, but it also puts forward strict requirements on the power consumption and heat dissipation of the chip.

In terms of performance, the first thing to consider is how two stacked chips can achieve performance superposition and how they can be compatible with each other and in parallel to maximize performance.

In terms of design, in addition to considering how to increase stacking chips on chips as big as the fingernail, power consumption and heat dissipation issues must also be considered!

For example, the Huyue 280 chip has 35W power, and if it is simply superimposed together, it has 70W power.

Generally, laptop CPUs have 35W power. If the power of stacked CPU is still 70W, how to solve the problem of heat dissipation at high power?

so.

Stacking technology sounds like superimposing two chips together, which is a simple packaging technology.

In fact, stacking technology is not only a packaging technology, but also a fusion of chip design and packaging technology. While solving stacking chips, it also requires taking into account various problems such as performance, power consumption, and heat dissipation.

Such a design, the packaging complexity and difficulty of designing a chip are naturally incomparable.

but.

Such top-notch technology is now in front of you.

【TSS-3.5D Vertical Chip Stacking Packaging Technology】:

3.5D vertical chip stacking packaging technology combines "heterogeneous chip technology" and "3.5D vertical packaging technology". After the new design is integrated, various chip combinations are packaged to form a 3.5D internal chip space to reduce heat dissipation and reduce heat dissipation.

Power consumption, purpose of improving chip performance.

[3.5D Packaging Technology]: After stacking, the comprehensive performance of the two main frequency chips can be improved by 80% and the power consumption is reduced by 75%.

Hu was overview of TSS-3.5D chip stacking and packaging technology and was filled with joy.

Although the 3.5D stacking technology can only increase the performance of two 28-nanometer chips after stacking to 80%, and the power consumption is only reduced by 75%, Hu Lai is still satisfied!

After all, laptops are different from mobile phones, and they are still acceptable if they consume more power!

Without hesitation, Hu Lai directly chose to buy [3.5D packaging technology!]

A strong light flashed, ten million points were deducted, and familiar system sounds came to my ears.

"Congratulations on your successful purchase of the 'TSS-3.5D vertical chip stacking packaging technology'. If you want to use the '3.5D stacking packaging technology', you need to redesign the specially stacked chip drawings in the system!"

During the process of understanding just now, Hu Lai guessed that this would be the case in his heart.

In other words, the previous Huyue 140 chips and Huyue 280 chips were just ordinary chip designs and cannot be packaged using stacking technology.

In the future, chips that need to use stack packaging technology will need to be redesigned.

soon.

Hu Lai found the 28-nanometer design chip drawings in the system and click to buy.

The 28-nanometer integral design drawing requires 250,000 points, choose the NB-Y architecture and choose the consumer-grade process.

This time, consumer-grade craftsmanship spent 100,000 points.

When clicking on Next, there is an additional option here:

"Does TSS-3.5D vertical chip stacking packaging technology be used?"

"yes!"

The picture flashed, and the chip design came to the last step: adjusting the chip performance.

This time Hu Lai has more experience. This time, the 28-nanometer stacked chip is mainly used on computers, so the size is not that important.

Last time he knew that the larger the chip size, the more transistors there will be, and the performance will naturally be stronger.

so.

After he specifically exited the system and asked the technical director of the Phoenix IT computer department, he obtained the maximum size that the Phoenix laptop CPU can be modified, and then entered the system for adjustment.

By fixing the power consumption at 45W and adjusting the chip size to the maximum acceptable range, the CPU performance is obviously improved on the floating screen.

In the end, a chip designed with 28nm stacking technology was successful.

Unnamed chip 1: "A chip with 28nm process and NB-Y architecture, default main frequency is 2.8GHZ, six-core and six-thread processor, computing power is 90TOPS, power consumption is 45W, maximum memory is 128GB, and independent graphics card is supported

!”

This time, the stacked chip is designed to be larger than the previous two chips. Because it is larger, it also brings performance improvements.

In this way, the most important main frequency performance is only 0.1GHZ lower than that of Huyue 140!

If you don’t say it strictly, the performance of the 28-nanometer stacked chip designed in front of you is almost no different from the previous Huyue 140 chip!

Hu was very satisfied with the performance in front of him, the absolute value of the tens of millions of points spent!

Not only is it worth it, he has realized that "3.5D vertical chip stacking packaging technology" is another technical route in the chip field!

It is no exaggeration to say that America has always used high-end processes to jamm the necks of Yanguo companies, and now, Phoenix also has a powerful weapon to jamm the American chips in its hands!

When Moore's Law comes to an end, when the 3-nanometer and 2-nanometer chip process process is finally difficult to break through.

And Phoenix masters 3.5D vertical chip stacking and packaging technology!

Now that Phoenix 28-nanometer stacked chip is paired with a future operating system, its performance is close to that of a 7-nanometer chip!

I won’t even wait too long. After I get 50 million points to buy a 14-nanometer lithography machine, I will use stacking packaging technology...

At that time, Phoenix's 14-nanometer chips could hang 5-nanometer chips from major chip companies!

I don’t know what kind of crazy it will be when American chip companies know that Phoenix has such stacking technology!

Soon, Hu Lai called Director Zhang.

A few simple sentences told Director Zhang about the principle of stacking technology, and then handed over the newly designed 28-nanometer chip drawings and packaging technology to his hands.

"Lao Zhang, this is a brand new 28nm chip design drawing, called him "Tiger Leap 280D", a chip that uses stacking technology."

"This time, you first apply for a patent for stacking technology, and then go to Mr. Liang Song, SMIC, and ask him to arrange a 28-nanometer production capacity."

"But, you know, this chip needs to be strictly confidential."

Director Zhang was shocked when he heard Hu Lai’s description of stacking technology, and he naturally knew that this matter was important.

He didn't delay, he said hello and left.

...

Time flies very quickly. As noon approaches, Hu Lai has received countless calls from friends, and even his leader Gao Ming personally called to express condolences.

Hu Lai, who found a solution to the dilemma, was already thinking about the next Phoenix plan.

The American blockade of Phoenix is ​​already on the surface, and the chip problem has not revolved at all.

Phoenix's first priority next is to collect 50 million points and truly solve the problem of 14-nanometer lithography machine!

Then, using a 14-nanometer lithography machine to use stacking technology to complete the process catching up, allowing Phoenix to have top chips with 3-nanometer and 5-nanometer performance!

Before he could figure out which step to start, Mr. Rebusley, who had called once in the morning, suddenly called.

As soon as he answered the phone, Rebs spoke in a low tone on the other end of the phone:

"Mr. Hu, the Winter Alliance formed by Mir and Inet just now, jointly issued a subsidy plan to all our host computer manufacturers."

"Their subsidy plan is obvious. Each manufacturer benchmarks the models of the 'Starry Sky' version and 'Starry Sky SE' version. Each unit sold subsidy of 300 yuan will be directly deducted from next year's WIN system authorization fee."

"Our rice notebook department also received a notice that they are targeting Phoenix notebooks."

"Also, just at 12 noon, the BookAir, which is priced at 7,999 yuan in comparison with Phoenix's Starry Sky, has also been reduced in its channel price. Now the price of Jingdong is only 7,199 yuan..."

Hu Lai was stunned and then laughed.

This time it's not only Mir and Inet, but Hongguo is also here?

This is a determined intention to completely block Phoenix Computer in all aspects!

...

PS: Thank you to Feng Yuehen, the big guy in the group, for giving you 2,000 yuan!
Chapter completed!